Conventionally, a matched filter has been used as a reverse spread means of the spread spectrum receiver. FIG. 18 shows a construction example of a conventional N-type matched filter. In FIG. 18, dm and rm respectively represent a spread spectrum receive signal and a correlation signal, and pn represents a spread code of period N (n=0, 1, 2, . . . , N−1). Assuming that an interval length (chip interval length) of the spread code pn is Tc, the receive signal dm is subjected to a sampling with the same period as the chip interval length Tc on a time series. Here, regarding the spread codes pn and pn+1, pn+1 precedes pn. In the case of other signals, for example, the receive signal dm precedes dm+1.
Assuming that an interval length (symbol interval length) is Ts regarding data subjected to spreading on a transmitting side, the relation of N=Ts/Tc is satisfied among a spread ratio N, the chip interval length Tc, and the symbol interval length Ts. As shown in FIG. 18, in the conventional matched filter, a tap number M equals to the spread ratio N. Hereinafter, for simple explanation on the operation, the receive signal dm is regarded as a baseband signal.
The delay circuit d is constituted by N−1 delay elements di (i=1, 2, . . . , N−1) connected in series. The receive signal dm is inputted to a delay element di. Each delay element di has a delay time equivalent to the chip interval length Tc. And then, outputs dm-i of the delay element di and the input signal dm are respectively multiplied by the spread code pn in multiplying circuits mn, all the outputs from the multiplying circuits are added to one another in an adding circuit k. Thus, the correlation signal rm is obtained relative to the section Ts corresponding to one period of the spread signal pn.
Conventionally, the spread signal pn is constituted only by two values of “+1” and “−1”, so that the conventional multiplying circuits mn reverse positive inputs and negative inputs transmitted to the adding circuit k in accordance with the spread code pn, and outputs the input signal dm and the outputs dm−i of the delay elements di. As illustrated in FIG. 18, in the matched filter, the spread code pn is fixed, and a cross-correlation function is computed relative to the receive signal dm shifted for every chip interval length Tc. When the phases of the receive signal dm and the spread code pn coincide with each other, an absolute value of the correlation signal rm rises to a maximum value. Due to periodicity of the receive signal dm and the spread code pn, the phases coincide with each other for every Ts of the symbol interval length. The point of coincidence serves as a synchronous phase and is used for synchronous capture and synchronous trace. Hence, reverse spread in the matched filter is always carried out with the interval Ts period corresponding to one period of the spread code pn, so that the stage for adjusting the phases of the receive signal dm and the spread code pn is not necessary.
Moreover, as another example of a matched filter used for a spread spectrum receiver, Japanese Published Unexamined Patent Publication No. 83486/1997 (Tokukaihei 9-83486, published on Mar. 28, 1997) discloses that a product-sum computing section is provided for performing weighted adding on a PN code to an analog input signal and for outputting the adding result as an analog output signal, the analog output of the product-sum computing section is held in an intermittent manner, a peak of the held analog signal is detected, a timing of the detected peak value is determined, the peak value of the analog signal is digitalized by an A/D converter only at a timing of the peak value.
This arrangement makes it possible to minimize the operating speed of the D/A convertor, thereby reducing power consumption.
Furthermore, as another example of the filter circuit, for example, “A 20-Msample/s Switched-Capacitor Finite-Impulse-Response Filter Using a Transposed Structure.” of IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 30, No. 12, DECEMBER 1995, P1350–1356 discloses that a switched capacitor circuit is used to form an FIR filter as shown in FIG. 19, an input signal vi is multiplied by coefficients a1 to a4, a partial correlation value is subjected to a four-stage analog adding by pipeline method, and a correlation value vo is outputted.
According to the technique disclosed in the above document, analog computing can be performed on a correlation value having a small number of taps, with small power consumption.
Additionally, as another example of the filter circuit, Japanese Published Examined Patent No. 2773075 discloses that a matched filter technique, in which a CCD serving as a charge transmitting element is used as an analog shift register to output a correlation value. This arrangement makes it possible to perform analog computing on a correlation value having a small number of taps, with small power consumption.
The matched filter is characterized by a short synchronous capture time. However, in this case, the circuit becomes larger. Namely, when the construction of FIG. 18 is realized in a digital circuit, the adding circuit k becomes larger. This is because a digital multiple-input adding circuit can be realized only by combination of two-input adding circuits. When the number of taps is N, at least N−1 two-input adding circuits are necessary. Further, the shorter the chip interval length Tc, the higher operating speed is required, resulting in larger power consumption.
Therefore, in order to solve the above problem, as disclosed in Japanese Published Unexamined Patent Publication No. 83486/1997 (Tokukaihei 9-83486, published on Mar. 28, 1997), attention has been directed toward an analog matched filter using a reverse amplifier circuit.
Although the construction disclosed in the above publication reduces power consumption of a baseband processing section by suppressing an operating speed of the A/D convertor, a circuit for inspecting a peak of an analog signal becomes complicated. Since a peak value of an analog output signal is detected and is subjected to A/D conversion, accuracy for detecting a peak value is low in spite of the complicated circuit. Consequently, an analog spread spectrum receive signal cannot be accurately modulated.
The construction of FIG. 19 has a small number of taps with four stages. Hence, a large dynamic range is not necessary for analog adders k1 to k4. However, for a matched filter, it is necessary to add a partial correlation value for 256 to 512 times. In such a construction with multiple stages, the analog adder requires a larger dynamic range at the later stages where a large number of the partial correlation values are cumulated, to prevent saturation of the cumulated partial correlation values. Therefore, the power consumption of the adder becomes larger. Meanwhile, when the level of the partial correlation value is set lower, it is possible to reduce the dynamic range of the adder; however, the A/D converter requires high resolution to convert a correlation output vo to a digital output so as to simplify the processing of the correlation output vo in the following circuits. Consequently, the construction becomes complicated and the power consumption is increased.
Moreover, regarding the construction disclosed in Japanese Published Examined Patent No. 2773075, any problem occurs in the case of the PN code having a small number of taps. However, for practical use as a matched filter, it is necessary to add a partial correlation value for 256 to 512 times and to cumulate a larger amount of charge, resulting in degradation in S/N.
The present invention is devised to solve the above problem. The objective is to provide a filter circuit which can reduce the size and power consumption of the circuit, improve accuracy of receiving a signal even when the circuit size and power consumption is small, and realize a simple signal processing in the following circuit.